1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device including a MOSFET formed on a thin-film SOI (Silicon On Insulator).
2. Description of the Background Art
A procedure for the formation of a MOSFET having a partial trench isolation structure on a thin film SOI in a conventional semiconductor device will be described.
First, a buried oxide film, an SOI layer, and an underlying oxide film are formed in the order named on a Si substrate. Next, an isolation oxide film is formed to extend through the underlying oxide film to some mid-portion in the SOI layer. Next, impurities are implanted as a channel dopant. Thereafter, the underlying oxide film is removed. Next, a gate oxide film and a gate polysilicon layer are formed on the SOI layer and the isolation oxide film, and are then patterned. Next, impurities are implanted onto the SOI layer to form an extension. Thereafter, an oxide film and a nitride film are formed. Next, anisotropic etching is performed on the oxide film and the nitride film to form sidewalls. Next, impurities are implanted to form a source/drain region in an upper portion of the SOI layer. The above-mentioned steps are executed to produce the MOSFET having the partial trench isolation structure.
Conventional methods of manufacturing MOSFETs or conventional partial trench isolation structures are disclosed in: Japanese Patent Application Laid-Open No. 5-218072 (1993); Japanese Patent Application Laid-Open No. 2004-31492; DIGEST OF TECHNICAL PAPERS, pp. 131-132, “Bulk-Layout-Compatible 0.18 μm SOI-CMOS Technology Using Body-Fixed Partial Trench Isolation (PTI)”, Y. Hirano, S. Maeda, T. Matsumoto, K. Nii, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, H. Kawashima, S. Maegawa, M. Inuishi and T. Nishimura, 1999 IEEE International SOI Conference, October 1999; DIGEST OF TECHNICAL PAPERS, pp. 154-155, “Impact of 0.18 μm SOI CMOS Technology using Hybrid Trench Isolation with High Resistivity Substrate on Embedded RF/Analog Applications”, S. Maeda, Y. Wada, K. Yamamoto, H. Komurasaki, T. Matsumoto, Y. Hirano, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, K. Ueda, K. Mashiko, S. Maegawa, and M. Uniishi, VLSI Technology, 2000 Symposium; and “80 nm CMOSFET Technology Using Double Offset-Implanted Source/Drain Extension and Low Temperature SiN Process”, H. Sayama, Y. Nishida, H. Oda, J. Tsuchimoto, H. Umeda, A. Teramoto, K. Eikyu, Y. Inoue and M. Inuishi, 2000 IEEE IEDM.
For the formation of the source/drain region in the conventional method of manufacturing the semiconductor device, implantation energy is adjusted so that the impurities reach the buried oxide film for the purpose of reduction in parasitic capacitance. However, the execution of the anisotropic etching on the oxide film and the nitride film during the formation of the sidewalls results in overetching to significantly reduce the thickness of the isolation oxide film. For this reason, when the impurities are implanted so as to reach the buried oxide film, the impurities penetrate through the isolation oxide film into the SOI layer lying under the isolation oxide film. Thus, the conventional method presents the problem of the occurrence of an isolation failure.
To prevent such an isolation failure, it is contemplated to decrease the impurity implantation energy. In such a case, however, another problem arises that the impurities for the formation of the source/drain region do not reach the buried oxide film to result in the increase in parasitic capacitance.